CIRCT - Design Hardware in Ruby

SEC-01 // Features

Everything you need to
design digital hardware.

数字硬件设计所需的一切

From high-level Ruby to synthesizable gates, CIRCT provides a complete hardware design pipeline.

Ruby DSL

Design hardware using Ruby's expressive syntax and metaprogramming. Familiar language, powerful abstractions.

Component Library

Gates, flip-flops, registers, ALU, memory modules, and more. Build complex designs from proven primitives.

Verilog/VHDL Import

Import existing Verilog and VHDL designs into RHDL. Integrate legacy IP, vendor cores, and third-party modules.

Fast Simulation

RTL and gate-level simulation powered by a Rust backend. WASM support enables in-browser testing.

Verilog Export

Generate clean, synthesizable Verilog HDL from your Ruby designs. Ready for FPGA synthesis and ASIC flows.

Gate Synthesis

Automatic lowering to primitive gates: AND, OR, XOR, NOT, MUX, and DFF. Full gate-level netlist generation.

Circuit Diagrams

Multi-level circuit visualization in SVG, PNG, and DOT formats. See your hardware at any abstraction level.

SEC-02 // Components

Four powerful
component abstractions.

四种强大的组件抽象

Combinational

Direct input-to-output mapping with expressions and case statements

Sequential

Clock-driven components with synchronous reset and enable signals

Memory

Synchronous write, asynchronous read RAM with configurable depth and width

State Machines

FSM with transition conditions, timed states, and output logic

SEC-03 // Architecture

CIRCT IR at the
center of everything.

CIRCT IR 是一切的核心

RHDL lowers to CIRCT IR. Verilog and VHDL import to it. Multiple execution backends fan out from this central representation.

RHDL

Ruby HDL lowering

Verilog / VHDL

Import existing HDL

CIRCT IR

Central representation

Verilator

Normalized Verilog

Arcilator

Arc simulation

Rust Compiler

Native execution

Full Architecture Details

SEC-04 // Code

Write hardware like
you write software.

像写软件一样写硬件

Familiar Ruby syntax with powerful hardware abstractions. No arcane HDL knowledge required.

simple_alu.rb
class SimpleALU < RHDL::Sim::Component
  input  :a, width: 8
  input  :b, width: 8
  input  :op, width: 2
  output :result, width: 8

  behavior do
    result <= case_select(op, {
      0 => a + b,
      1 => a - b,
      2 => a & b,
      3 => a | b
    }, default: 0)
  end
end
simple_alu.vGenerated Verilog
module SimpleALU (
  input  [7:0] a,
  input  [7:0] b,
  input  [1:0] op,
  output reg [7:0] result
);

always @(*) begin
  case (op)
    2'b00: result = a + b;
    2'b01: result = a - b;
    2'b10: result = a & b;
    2'b11: result = a | b;
    default: result = 8'b0;
  endcase
end

endmodule

            
              ALU Deep Dive
              
            
          

counter.rb
class Counter < RHDL::Sim::SequentialComponent
  input  :clk, :rst, :en
  output :count, width: 8

  sequential clock: :clk,
             reset: :rst,
             reset_values: { count: 0 } do
    count <= mux(en, count + 1, count)
  end
end
counter.vGenerated Verilog
module Counter (
  input        clk,
  input        rst,
  input        en,
  output reg [7:0] count
);

always @(posedge clk or posedge rst) begin
  if (rst)
    count <= 8'b0;
  else if (en)
    count <= count + 1;
end

endmodule

            
              Counter Deep Dive
              
            
          

ram.rb
class RAM256x8 < RHDL::Sim::Component
  include RHDL::DSL::Memory

  input  :clk, :we
  input  :addr, width: 8
  input  :din,  width: 8
  output :dout, width: 8

  memory :mem, depth: 256, width: 8

  sync_write  :mem,
    clock: :clk, enable: :we,
    addr:  :addr, data: :din

  async_read  :dout,
    from: :mem, addr: :addr
end
ram.vGenerated Verilog
module RAM256x8 (
  input        clk,
  input        we,
  input  [7:0] addr,
  input  [7:0] din,
  output [7:0] dout
);

reg [7:0] mem [0:255];

assign dout = mem[addr];

always @(posedge clk) begin
  if (we)
    mem[addr] <= din;
end

endmodule

            
              Memory Deep Dive
              
            
          